In the semiconductor fabrication process, a series of steps is performed to form connections between the devices after they arc finished. The connection forming process is a vital element in determining the operation of the devices. Every connection to the individual device and region must be formed with low resistance and leakage. Any undesired connecting between individual circuit path might cause the incorrect operation of the circuits and the fail or damage of the devices. With the progressing of the semiconductor integrated circuits to the ULSI (ultra large scale integration) level, the connections must be formed with less defects. Thus the accuracy, quality, and reliability of the connections must be raised.
In general, the connections on the integrated circuits are formed with multiple layers which are stacked sequentially over the semiconductor substrate. The materials of the connections can include conductive materials like polysilicon, aluminum, titanium, aluminum, tungsten suicide, and etc. Each layer of connections can be formed of a single material, or a combination of different conductive materials.
Without limiting the scope of the present invention, the background of the invention is illustrated with the formation of the first interconnection layer on a semiconductor. Referring to FIG. 1, a semiconductor substrate 10 with a gate structure 12 formed over is illustrated. A pad insulator 14 like oxide is formed between the semiconductor substrate 10 and the gate structure 12 to serve as a gate insulator. The gate structure 12 is formed for the fabrication of active devices. The gate structure 12 with a combination of layers is employed in most conventional semiconductor fabrication process. As an example, the gate structure 12 can be a combination of a polysilicon layer 16, a tungsten silicide layer 18, and an insulator including 20 and 22. The insulator 20 and 22 formed respectively on top and sidewall of the polysilicon layer 16 and the tungsten silicide layer 18 can be nitride for insulating the conductive gate.
The polysilicon layer 16, the tungsten silicide layer 18, and the top insulator 22 in the stacked combination have diverse physical and chemical properties. The combined structure need to be processed with multiple clean steps before the formation of the sidewall insulator 22. Under the different physical and chemical properties, some lateral portion of the tungsten silicide layer 18 is removed in the clean steps. A tungsten silicide layer 18 narrower than the polysilicon layer 16 and the top insulator 22 can be found as shown in FIG. 1. The sidewall insulator 22 is formed conformably on the sidewall of the stacked combination. Thus a recessed region 22a on the sidewall of the sidewall insulator 22 is formed.
For forming the first connection layer, a dielectric layer 24 is then deposited over the gate structure 12 and the semiconductor substrate 10, as shown in FIG. 2. An oxide layer deposited with chemical vapor deposition (CVD) is employed. With the conformability of the oxide layer 24, the profile of the sidewall insulator 22 with a duplicated recessed region 24a is formed. For a widely applied reaction gas of tetra-ethyl-ortho-silicate (TEOS) in the CVD process, the recess problem is further enhanced for the better conformability of the TEOS oxide layer 24. A conductive layer 26 is then formed over the oxide layer 24. A portion of the conductive layer 26 is removed with a patterning process to define the pattern of interconnections. A portion of the conductive layer 26, the residue 26a, is left within the recessed region on the sidewall of the oxide layer 24 due to the lateral recessed profile.
The residue 26a on the sidewall causes the hazard of short connections between the individual circuit paths defined on the conductive layer 26. The short connection is formed when two individual paths cross over a common residue 26a and form a electrically conductive connection through the conductive residue 26a. The short connections on the integrated circuits ruined the design of the circuits and cause the unexpected operation of the devices. Thus lots of devices with embedded and unrecoverable operational failures can be formed. The yield of the semiconductor manufacturing process is influenced considerably at the same time.